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ltc6081/ltc6082 1 60812fa typical application features applications description precision dual/quad cmos rail-to-rail input/ output ampli ers the ltc ? 6081/ltc6082 are dual/quad low offset, low drift, low noise cmos operational ampli? ers with rail-to-rail input/output swing. the 70v maximum offset, 1pa input bias current, 120db open loop gain and 1.3v p-p 0.1hz to 10hz noise make it perfect for precision signal conditioning. the ltc6081/ ltc6082 features 100db cmrr and 98db psrr. each ampli? er consumes only 330a of current on a 3v supply. the 10-lead dfn has an independent shutdown function that reduces each ampli? ers supply current to 1a. ltc6081/ltc6082 is speci? ed for power supply voltages of 3v and 5v from C40c to 125c. the dual ltc6081 is available in 8-lead msop and 10-lead dfn10 packages. the quad ltc6082 is available in 16-lead ssop and dfn packages. shock sensor ampli? er (accelerometer) maximum offset voltage: 70v (25c) maximum offset drift: 0.8v/c maximum input bias: 1pa (25c) 40pa (t a 85c) open loop voltage gain: 120db typ gain bandwidth product: 3.6mhz cmrr: 100db min psrr: 98db min 0.1hz to 10hz noise: 1.3v p-p supply current: 330a rail-to-rail inputs and outputs unity gain stable 2.7v to 5.5v operation voltage dual ltc6081 in 8-lead msop and 10-lead dfn10 packages; quad ltc6082 in 16-lead ssop and dfn packages photodiode ampli? er strain gauge high impedance sensor ampli? er microvolt accuracy threshold detection instrumentation ampli? ers thermocouple ampli? ers 60812 ta01 v + v + 1g 2m 1m 10k 3.9pf 47pf 0.1 f 1/2 ltc6081 0.1 f 8.2pf 2m 3.9pf 1m v out = 109mv/g bw ~ 2.2khz murata pkgs-00ld 770pf 0 sensor v os drift histogram v osdrift ( v/ c) number of amplifiers (out of 100) 30 25 20 15 10 5 0 60812 ta01b ltc6081ms8 t a = ?0 c to 125 c v s = 3v v cm = 0.5v 0.20 0.30 ?.10 ?.20 0 0.10 l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners.
ltc6081/ltc6082 2 60812fa pin configuration absolute maximum ratings (note 1) top view dd package 10-lead (3mm 3mm) plastic dfn 10 9 6 7 8 4 5 3 2 1 v + outb ?nb +inb shdn_b outa ?na +ina v shdn_a b a t jmax = 125c, ja = 43c/w underside metal connected to v C 1 2 3 4 outa ?na +ina v 8 7 6 5 v + outb ?nb +inb top view ms8 package 8-lead plastic msop b a t jmax = 150c, ja = 200c/w 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 outd ?nd +ind v +inc ?nc outc nc outa ?na +ina v + +inb ?nb outb nc top view dhc package 16-lead (5mm 3mm) plastic dfn d a c b t jmax = 125c, ja = 43c/w underside metal connected to v C gn package 16-lead plastic ssop 1 2 3 4 5 6 7 8 top view 16 15 14 13 12 11 10 9 outa ?na +ina v + +inb ?nb outb nc outd ?nd +ind v +inc ?nc outc nc d a c b t jmax = 150c, ja = 110c/w total supply voltage (v + to v C ) ...................................6v input voltage ...................................................... v C to v + output short circuit duration (note 2)............. inde? nite operating temperature range (note 3) ltc6081c, ltc6082c .......................... C40c to 85c ltc6081i, ltc6082i ............................. C40c to 85c ltc6081h, ltc6082h ........................ C40c to 125c (h temperature range not available in dfn package) speci? ed temperature range (note 4) ltc6081c, ltc6082c .............................. 0c to 70c ltc6081i, ltc6082i ............................. C40c to 85c ltc6081h, ltc6082h ........................ C40c to 125c junction temperature dfn packages ................................................... 125c all other packages ............................................ 150c storage temperature range dfn packages .................................... C65c to 125c all other packages ............................. C65c to 150c lead temperature (soldering, 10 sec) .................. 300c
ltc6081/ltc6082 3 60812fa order information lead free finish tape and reel part marking* package description specified temperature range lt6081cdd#pbf lt6081cdd#trpbf lcjp 10-lead (3mm 3mm) plastic dfn 0c to 70c lt6081idd#pbf lt6081idd#trpbf lcjp 10-lead (3mm 3mm) plastic dfn C40c to 85c lt6081cms8#pbf lt6081cms8#trpbf ltcjn 8-lead plastic msop 0c to 70c lt6081ims8#pbf lt6081ims8#trpbf ltcjn 8-lead plastic msop C40c to 85c lt6081hms8#pbf lt6081hms8#trpbf ltcjn 8-lead plastic msop C40c to 125c lt6082cdhc#pbf lt6082cdhc#trpbf 6082 16-lead (5mm 3mm) plastic dfn 0c to 70c lt6082idhc#pbf lt6082idhc#trpbf 6082 16-lead (5mm 3mm) plastic dfn C40c to 85c lt6082cgn#pbf lt6082cgn#trpbf 6082 16-lead plastic ssop 0c to 70c lt6082ign#pbf lt6082ign#trpbf 6082i 16-lead plastic ssop C40c to 85c lt6082hgn#pbf lt6082hgn#trpbf 6082h 16-lead plastic ssop C40c to 125c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/
ltc6081/ltc6082 4 60812fa electrical characteristics the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. test conditions are v + = 3v, v C = 0v, v cm = 0.5v unless otherwise noted. symbol param eter conditions c, i suffixes h suffix units min typ max min typ max v os offset voltage ltc6081ms8, ltc6082gn v cm = 0.5v, 2.5v ltc6081ms8, ltc6082gn v cm = 0.5v, 2.5v ltc6081dd, ltc6082dhc v cm = 0.5v, 2.5v ltc6081dd, ltc6082dhc v cm = 0.5v, 2.5v C70 C90 C70 C90 70 90 70 90 C70 C90 70 90 v v v v v os ? t input offset voltage drift (note 5) 0.2 0.8 0.2 0.8 v/c i b input bias current (note 6) 0.2 1 40 0.2 1 500 pa pa i os input offset current 0.1 15 0.1 100 pa pa e n input referred noise noise density at f = 1khz integrated noise from 0.1hz to 10hz 13 1.3 13 1.3 nv/hz v p-p i n input noise current density (note 7) 0.5 0.5 fa/hz input common mode range v C v + v C v + v c diff differential input capacitance 3 3 pf c cm common mode input capacitance 77pf cmrr common mode rejection ratio v cm = 0v to 1.5v v cm = 0v to 1.5v v cm = 0v to 3v v cm = 0v to 3v 95 88 93 88 105 100 105 100 95 86 93 86 105 100 105 100 db db db db psrr power supply rejection ratio v s = 2.7v to 5.5v 98 96 110 98 96 110 db db v out output voltage, high, either output pin no load i source = 0.5ma i source = 5ma C32 C320 1 C35 C350 1mv mv mv output voltage, low, either output pin (referred to v C ) no load i sink = 0.5ma i sink = 5ma 1 33 300 1 40 360 mv mv mv a vol large-signal voltage gain r load = 10k, 0.5v < v out < 2.5v 110 120 110 120 db i sc output short-circuit current source sink 17 17 15 15 ma ma sr slew rate a v = 1 1 1 v/s gbw gain-bandwidth product (f test = 50khz) r l = 100k 2.5 1.8 3.6 2.5 1.5 3.6 mhz mhz 0 phase margin r l = 10k 70 70 deg t s settling time 0.1% a v = 1, 1v step 6 6 s i s supply current (per ampli? er) no load 330 400 435 330 400 460 a a shutdown current (per ampli? er) shutdown, v ? s ? h ? d ? n 0.8v 0.5 2 a a v s supply voltage range guaranteed by the psrr test 2.7 5.5 2.7 5.5 v channel separation f s = 10khz, r l = 10k C120 C120 db
ltc6081/ltc6082 5 60812fa electrical characteristics the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. test conditions are v + = 3v, v C = 0v, v cm = 0.5v unless otherwise noted. symbol param eter conditions c, i suffixes h suffix units min typ max min typ max shutdown logic ? s ? h ? d ? n high ? s ? h ? d ? n low 2 0.8 2 0.8 v v thd total harmonic distortion f = 10khz, v + = 3v, v out = 1v p-p , r l = 10k C90 C90 db t on turn-on time v ? s ? h ? d ? n = 0.8v to 2v 10 10 s t off turn-off time v ? s ? h ? d ? n = 2v to 0.8v 2 2 s ? s ? h ? d ? n pin current v ? s ? h ? d ? n = 0v 2a the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. test conditions are v + = 5v, v C = 0v, v cm = 0.5v unless otherwise noted. symbol param eter conditions c, i suffixes h suffix units min typ max min typ max v os offset voltage ltc6081ms8, ltc6082gn v cm = 0.5v ltc6081ms8, ltc6082gn v cm = 0.5v ltc6081dd, ltc6082dhc v cm = 0.5v ltc6081dd, ltc6082dhc v cm = 0.5v C70 C90 C70 C90 70 90 70 90 C70 C90 70 90 v v v v v os ? t input offset voltage drift (note 8) 0.2 0.8 0.2 0.8 v/c i b input bias current 0.2 40 0.2 500 pa pa i os input offset current 0.1 15 0.1 100 pa pa e n input referred noise f = 1khz 0.1hz to 10hz 13 1.3 13 1.3 nv/hz v p-p i n input noise current density (note 7) 0.5 0.5 fa/hz input common mode range v C v + v C v + v c diff differential input capacitance 3 3 pf c cm common mode input capacitance 77pf cmrr common mode rejection ratio v cm = 0v to 3.5v v cm = 0v to 3.5v v cm = 0v to 5v 100 95 86 110 110 95 100 94 86 110 110 95 db db db psrr power supply rejection ratio v s = 2.7v to 5.5v 98 96 110 98 96 110 db db v out output voltage, high, either output pin (referred to v + ) no load i source = 0.5ma i source = 5ma C24 C200 1 C25 C220 1mv mv mv output voltage, low, either output pin (referred to v C ) no load i sink = 0.5ma i sink = 5ma 1 27 210 1 32 240 mv mv mv a vol large-signal voltage gain r load = 10k, 0.5v < v out < 4.5v 110 120 110 120 db
ltc6081/ltc6082 6 60812fa the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. test conditions are v + = 5v, v C = 0v, v cm = 0.5v unless otherwise noted. note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: a heat sink may be required to keep the junction temperature below the absolute maximum. this depends on the power supply voltage and how many ampli? ers are shorted. note 3: the ltc6081c/ltc6082c and ltc6081i/ltc6082i are guaranteed functional over the operating temperature range of C40c to 85c. the ltc6081h/ltc6082h are guaranteed functional over the operating temperature range of C40c to 125c. note 4: the ltc6081c/ltc6082c are guaranteed to meet speci? ed performance from 0c to 70c. the ltc6081c/ltc6082c are designed, electrical characteristics symbol param eter conditions c, i suffixes h suffix units min typ max min typ max i sc output short-circuit current source sink 24 24 21 21 ma ma sr slew rate a v = 1 1 1 v/s gbw gain-bandwidth product (f test = 50khz) r l = 100k 2.5 1.8 3.5 2.5 1.5 3.5 mhz mhz 0 phase margin r l = 10k 70 70 deg t s settling time 0.1% a v = 1, 1v step 6 6 s i s supply current (per ampli? er) no load 340 425 465 340 425 490 a a shutdown current (per ampli? er) shutdown, v ? s ? h ? d ? n 1.2v 6a v s supply voltage range guaranteed by the psrr test 2.7 5.5 2.7 5.5 v channel separation f s = 10khz, r l = 10k C120 C120 db shutdown logic ? s ? h ? d ? n high ? s ? h ? d ? n low 3.5 1.2 3.5 1.2 v v thd total harmonic distortion f = 10khz, v + = 5v, v out = 2v p-p , r l = 10k C90 C90 db t on turn-on time v ? s ? h ? d ? n = 1.2v to 3.5v 10 10 s t off turn-off time v ? s ? h ? d ? n = 3.5v to 1.2v 2 2 s ? s ? h ? d ? n pin current v ? s ? h ? d ? n = 0v 2a characterized and expected to meet speci? ed performance from C40c to 85c but are not tested or qa sampled at these temperatures. the ltc6081i/ltc6082i are guaranteed to meet speci? ed performance from C40c to 85c. the ltc6081h/ltc6082h are guaranteed to meet speci? ed performance from C40c to 125c. note 5: input offset drift is computed from the limits of the v os test divided by the temperature range. this is a conservative estimate of worst case drift. consult the typical performance characteristics section for more information on input offset drift. note 6: i b guaranteed by the v s = 5v test. note 7: current noise is calculated from i n = 2qi b , where q = 1.6 ? 10 C19 coulomb. note 8: v os drift is guaranteed by the v s = 3v test.
ltc6081/ltc6082 7 60812fa frequency (hz) noise voltage (nv/ hz) 1 110 100 90 80 70 60 50 40 30 20 10 0 100 1k 100k 60812 g09 10 10k v s = 3v v cm = 0.5v v s = 5v v cm = 0.5v t a = 25 c time after power up (s) 0 change in offset voltage ( v) 60 60812 g08 35 30 25 20 10 15 5 50 55 40 45 25 20 15 10 5 0 ? t a = 25 c v cm = 0.5v v s = 3v v s = 5v v cm (v) 0 v os ( v) 45 23 1 60812 g06 140 120 100 80 ?0 ?0 20 0 40 60 v s = 5v t a = 25 c representative parts v cm (v) 0 v os ( v) 2.5 3.0 1.5 2.0 0.5 1.0 60812 g05 40 30 20 10 ?0 ?0 ?0 ?0 0 v s = 3v t a = 25 c representative parts v osdrift ( v/ c) number of amps (out of 100) 30 25 20 15 10 5 0 0.20 60812 g01 0.30 ?.10 ?.20 0 0.10 ltc6081ms8 t a = ?0 c to 125 c v s = 3v v cm = 0.5v v osdrift ( v/ c) number of amps (out of 100) 25 20 15 10 5 0 60812 g02 0.20 ?.10 ?.20 ?.30 0 0.10 ltc6081dfn t a = ?0 c to 125 c v s = 3v v cm = 0.5v temperature ( c) ?0 v os ( v) 110 130 60812 g03 ?0 30 70 90 ?0 10 50 25 20 15 10 5 0 ? ?0 ?5 ?0 ltc6081ms8 v s = 3v v cm = 0.5v representative parts typical performance characteristics v os drift histogram v os drift histogram v os vs temperature v os histogram v os vs v cm v os vs v cm v os vs output current warm-up drift vs time noise voltage vs frequency v os ( v) number of amps (out of 100) 6.5 60812 g04 10.5 ?.5 ?.5 ?.5 2.5 ltc6081ms8 t a = 25 c v s = 3v v cm = 0.5v 18 16 14 12 10 8 6 4 2 0 output current (ma) ? v os ( v) 46 60812 g07 ? 2 0 ? 200 150 100 50 0 ?0 ?00 v s = 5v v cm = 2.5v t a = 125 c t a = 25 c t a = 55 c sinking current sourcing current
ltc6081/ltc6082 8 60812fa capacitive load (pf) 10 55 50 45 40 35 30 25 20 15 10 5 0 overshoot (%) 10000 60812 g18 100 1000 t a = 25 c v s = 3v v cm = 0.5v a v = 1 a v = 10 v cm (v) 0 i bias (pa) 4.0 5.0 4.5 60812 g14 1.0 2.0 3.0 3.5 0.5 1.5 2.5 40 30 20 10 ?0 ?0 ?0 ?0 0 ?0 ltc6081ms8 v s = 5v t a = 85 c t a = 70 c temperature ( c) 1000 100 10 1 0.1 20 40 60 80 100 120 140 60812 g13 input bias current (pa) v s = 5v v cm = 2.5v time (s) 0 output noise (1 v/div) 50 60812 g12 35 30 25 20 10 15 54045 t a = 25 c v s = 3v v cm = 2.5v frequency (hz) noise voltage (nv/ hz) 1 300 100 80 60 40 20 200 180 160 140 120 280 260 240 220 0 100 1k 100k 60812 g10 10 10k v s = 3v t a = 25 c pmos inputs v cm = 0.5v nmos inputs v cm = 2.5v typical performance characteristics noise voltage vs frequency 0.1hz to 10hz output voltage noise 0.1hz to 10hz output voltage noise input bias current vs temperature i bias vs v cm i bias vs v cm large signal transient small signal transient overshoot vs c l time (s) 0 output noise (500nv/div) 50 60812 g11 35 30 25 20 10 15 54045 t a = 25 c v s = 3v v cm = 0.5v v cm (v) 0 i bias (pa) 4.0 5.0 4.5 60812 g15 1.0 2.0 3.0 3.5 0.5 1.5 2.5 500 400 300 200 100 ?00 ?00 ?00 ?00 0 ?00 ltc6081ms8 v s = 5v t a = 125 c 200 s/div 0.5v/div 60812 g16 t a = 25 c v s = 1.5v r l = 10k c l = 100pf gnd 20 s/div 20mv/div 60812 g17 t a = 25 c v s = 1.5v r l = 10k c l = 100pf gnd
ltc6081/ltc6082 9 60812fa frequency (hz) gain (db) 60 ?0 ?0 40 20 0 phase (deg) 180 ?70 ?80 ?0 90 ?50 ?60 0 1m 100m 60812 g25 10m 1k 100k 10k v s = 5v v cm = 0.5v t a = 25 c c l = 200pf phase gain r l = 10k r l = 100k frequency (hz) 100 1k 10k 100k 1m 10m 100m psrr (db) 60812 g27 120 100 80 60 40 0 ?0 20 v s = 5v v cm = 0.5v t a = 25 c frequency (hz) 100 1k 10k 100k 1m 10m 100m cmrr (db) 60812 g26 120 100 80 60 40 0 ?0 20 v s = 5v v cm = 0.5v t a = 25 c r l = 1k frequency (hz) gain (db) 60 ?0 ?0 40 20 0 phase (deg) 270 ?70 ?80 180 ?0 90 ?60 0 1m 100m 60812 g24 10m 1k 100k 10k v s = 5v v cm = 0.5v t a = 25 c phase gain r l = 10k r l = 100k output voltage (v) 0 input voltage ( v) 2.5 3.0 1.5 2.0 0.5 1.0 60812 g22 20 10 ?0 ?0 ?0 ?0 0 v s = 3v t a = 25 c r l = 100k r l = 10k r l = 2k time ( s) 0 supply current opamp ( a) 500 60812 g20 300 200 100 400 1600 1200 800 400 0 supply voltage (v) 4 3 2 1 0 t a = 25 c no bypass capacitor supply voltage supply current temperature ( c) ?0 supply current ( a) 110 125 60812 g19 ?0 20 50 65 80 95 ?5 5 35 390 370 350 330 290 310 270 250 v cm = 0.5v per amplifier v s = 3v v s = 5v typical performance characteristics supply current vs temperature supply current vs time output impedance vs frequency open loop gain open loop gain open loop gain vs frequency open loop gain vs frequency cmrr vs frequency psrr vs frequency frequency (hz) 100 1k 10k 100k 1m 10m 100m output impedance ( ) 60812 g21 1000 100 10 1 0.1 0.01 v s = 3v v cm = 0.5v t a = 25 c a v = 100 a v = 10 a v = 1 output voltage (v) 0 input voltage ( v) 4.5 5.0 3.5 4.0 2.5 3.0 1.5 2.0 0.5 1.0 60812 g23 20 10 ?0 ?0 ?0 ?0 0 v s = 5v t a = 25 c r l = 100k r l = 10k r l = 2k
ltc6081/ltc6082 10 60812fa pin functions out: ampli? er output Cin: inverting input +in: noninverting input v + : positive supply v C : negative supply ? s ? h ? d ? n ? _ ? a: shutdown pin of ampli? er a, active low and only valid for ltc6081dd. an internal current source pulls the pin to v + when ? oating. ? s ? h ? d ? n ? _ ? b: shutdown pin of ampli? er b, active low and only valid for ltc6081dd. an internal current source pulls the pin to v + when ? oating. nc: not internally connected. exposed pad: connected to v C . typical performance characteristics channel separation vs frequency output voltage swing vs load current distortion vs frequency frequency (hz) 100 1k 10k 100k 1m 10m 100m channel separation (db) 60812 g28 0 ?00 ?0 ?0 ?0 ?40 ?20 ?0 v s = 3v v cm = 0.5v r l = 10k load current (ma) output voltage swing (v) (referred to supply voltage) +v s +v s ?.5 +v s ?.5 +v s ?.0 +v s ?.0 ? s 2.0 ? s 1.5 ? s 1.0 ? s 0.5 ? s 0 0.01 1 10 100 60789 g29 0.1 v s = 3v v cm = 0.5v source sink t a = 125 c t a = 25 c t a = ?5 c frequency (khz) 1 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 distortion (dbc) 1000 60812 g30 10 100 v s = 5v a v = 1 r l = 10k v out = 2v p-p 2nd 3rd
ltc6081/ltc6082 11 60812fa ?5 percentage of units 0.30 0.25 0.20 0.15 0.10 0.5 0 60812 f01 ?2 ? ? ? 0 v os change ( v) 15 12 9 36 v os change after 3 thermal cycles v cm = 0.5v v + = 3v 300 units applications information preserving input precision preserving input accuracy of the ltc6081/ltc6082 re- quires that the application circuit and pc board layout do not introduce errors comparable or greater than the 5v typical offset of the ampli? ers. temperature differentials across the input connections can generate thermocouple voltages of 10s of microvolts so the connections to the input leads should be short, close together and away from heat dissipating components. air current across the board can also generate temperature differentials. the extremely low input bias currents (0.1pa typical) al- low high accuracy to be maintained with high impedance sources and feedback resistors. leakage currents on the pc board can be higher than the input bias current. for example, 10g of leakage between a 5v supply lead and an input lead will generate 500pa! surround the input leads with a guard ring driven to the same potential as the input common mode voltage to avoid excessive leakage in high impedance applications. capacitive load ltc6081/ltc6082 can drive capactive load up to 200pf in unity gain. the capacitive load driving capability increases as the ampli? er is used in higher gain con? gurations. a small series resistance between the output and the load further increases the amount of capacitance the ampli? er can drive. ? s ? h ? d ? n pins pins 5 and 6 are used for power shutdown on the ltc6081 in the dd package. if they are ? oating, internal current sources pull pins 5 and 6 to v + and the ampli? ers operate normally. in shutdown, the ampli? er output is high imped- ance, and each ampli? er draws less than 2a current. rail-to-rail input the input stage of ltc6081/ltc6082 combines both pmos and nmos differential pairs, extending its input common mode voltage range to both positive and negative supply voltages. at high input common mode range, the nmos pair is on. at low common mode range, the pmos pair is on. the transition happens when the common voltage is between 1.3v and 0.9v below the positive supply. ltc6081 has better low frequency noise performance with pmos input on due to its lower ? icker noise (see voltage noise vs frequency and 0.1hz to 10hz input voltage noise in typical performance characteristics). thermal hysteresis figure 1 shows the input offset voltage hysteresis of the ltc6081ims8 for 3 thermal cycles from C45c to 90c. the typical offset shift is 4v. the data was taken with the ics in stress free sockets. mounting to pc boards may cause additional hysteresis due to mechanical stress. the ltc6081 will meet offset voltage speci? cations in the electrical characteristics table even after 15v of additional error from thermal hysteresis. figure 1. v os thermal hysteresis of ltc6081ms8
ltc6081/ltc6082 12 60812fa pc board layout mechanical stress on a pc board and soldering-induced stress can cause the v os and v os drift to shift. the dd and dhc packages are more sensitive to stress. a simple way to reduce the stress-related shifts is to mount the ic near the short edge of the pc board, or in a corner. the board edge acts as a stress boundary, or a region where the ? exure of the board is minimum. the package should always be mounted so that the leads absorb the stress applications information figure 2. vertical orientation of ltc6081dd with slots 60812 f02 long dimension slots and not the package. the package is generally aligned with the leads perpendicular to the long side of the pc board (see figure 2). the most effective technique to relieve the pc board stress is to cut slots in the board around the op amp. these slots can be cut on three sides of the ic and the leads can exit on the fourth side. figure 2 shows the layout of a ltc6081dd with slots at three sides.
ltc6081/ltc6082 13 60812fa simpli? ed schematic of the ampli? er r1 r2 r3 v + v r4 + d8 d7 out m8 m9 c1 c2 60812 ss v + v d5 d6 + output control m4 m6 a1 a2 m7 m5 i1 v bias m1 m2 m3 ?n v + v v + v d3 d4 +in v m11 m10 1 a i2 v + v d1 d2 shdn bias generation note: shdn is only available in the dfn10 package simplified schematic
ltc6081/ltc6082 14 60812fa typical applications low side current sense 60812 ta03 v dd + v + 15pf 1k 100k r sh v out = r sh ?i ?101 e noise = 3 v p-p , rti bw ~ 1khz load i 1/2 ltc6081 60812 ta04 v + 100k v out = 1011 ?v in v + + 1m 100k gain trim cmrr trim 50k 100k 0.1 f 0.1 f 1.96k 976k v in + 1/2 ltc6081 1/2 ltc6081 two op-amp instrumentation ampli? er
ltc6081/ltc6082 15 60812fa 60812 ta05 5v 5v + 1m 1m 10k 0.1 f 1 f 2.49m v out = 10mv/ c 0 c to 500 c 100pf k lt1025 r sensor: omega 5tc-tt-k-30-36 k-type thermocouple 1m resistors protect circuit to 350v with no phase reversal of amplifier output 1pa max i bias translates to 0.05 c error 20 v v os 0.5 c offset 1/2 ltc6081 typical applications thermocouple ampli? er precision nanoamp bidirectional current source ?.5v 2.5v 60812 ta06 + 0.01 f 0.1 f 0.1 f i out = ?na 1na for v in = ?0v 10v total error < 1% (10pa) i out v in + 100k 100k 100k 100 97.6k 10-turn 5k + 100k 1k 100 10m 3.9pf load 1/4 ltc6082 1/4 ltc6082 1/4 ltc6082 gain trim
ltc6081/ltc6082 16 60812fa package description 3.00 p 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-2). check the ltc website data sheet for current status of variation assignment 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 p 0.10 bottom viewexposed pad 1.65 p 0.10 (2 sides) 0.75 p 0.05 r = 0.125 typ 2.38 p 0.10 (2 sides) 1 5 10 6 pin 1 top mark (see note 6) 0.200 ref 0.00 C 0.05 (dd) dfn rev b 0309 0.25 p 0.05 2.38 p 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 p 0.05 (2 sides) 2.15 p 0.05 0.50 bsc 0.70 p 0.05 3.55 p 0.05 package outline 0.25 p 0.05 0.50 bsc dd package 10-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1699 rev b)
ltc6081/ltc6082 17 60812fa package description dhc package 16-lead plastic dfn (5mm 3mm) (reference ltc dwg # 05-08-1706) 3.00 0.10 (2 sides) 5.00 0.10 (2 sides) note: 1. drawing proposed to be made variation of version (wjed-1) in jedec package outline mo-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?xposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.115 typ r = 0.20 typ 4.40 0.10 (2 sides) 1 8 16 9 pin 1 top mark (see note 6) 0.200 ref 0.00 ?0.05 (dhc16) dfn 1103 0.25 0.05 pin 1 notch 0.50 bsc 4.40 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.20 0.05 0.50 bsc 0.65 0.05 3.50 0.05 package outline 0.25 0.05
ltc6081/ltc6082 18 60812fa package description gn16 (ssop) 0204 12 3 4 5 6 7 8 .229 ?.244 (5.817 ?6.198) .150 ?.157** (3.810 ?3.988) 16 15 14 13 .189 ?.196* (4.801 ?4.978) 12 11 10 9 .016 ?.050 (0.406 ?1.270) .015 .004 (0.38 0.10) 45 0 ?8 typ .007 ?.0098 (0.178 ?0.249) .0532 ?.0688 (1.35 ?1.75) .008 ?.012 (0.203 ?0.305) typ .004 ?.0098 (0.102 ?0.249) .0250 (0.635) bsc .009 (0.229) ref .254 min recommended solder pad layout .150 ?.165 .0250 bsc .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale gn package 16-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641)
ltc6081/ltc6082 19 60812fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description msop (ms8) 0307 rev f 0.53 0.152 (.021 .006) seating plane note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.18 (.007) 0.254 (.010) 1.10 (.043) max 0.22 ?0.38 (.009 ?.015) typ 0.1016 0.0508 (.004 .002) 0.86 (.034) ref 0.65 (.0256) bsc 0 ?6 typ detail ? detail ? gauge plane 12 3 4 4.90 0.152 (.193 .006) 8 7 6 5 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) 0.52 (.0205) ref 5.23 (.206) min 3.20 ?3.45 (.126 ?.136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.42 0.038 (.0165 .0015) typ 0.65 (.0256) bsc ms8 package 8-lead plastic msop (reference ltc dwg # 05-08-1660 rev f)
ltc6081/ltc6082 20 60812fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2007 lt 0809 rev a ? printed in usa related parts typical application part number description comments lt1678/lt1679 dual/quad precision op amps low noise, 2.7v to 36v operation ltc2050 zero-drift op amp 2.7v operation, sot-23 package ltc2051/ltc2052 dual/quad zero-drift op amps ms8/gn16 packages ltc2054/ltc2055 single/dual zero-drift op amp micropower, sot-23 and dfn packages ltc6078/ltc6079 dual/quad low noise precision cmos op amps micropower 0.7v/c v os drift ltc6241/ltc6242 dual/quad low noise cmos op amps 18mhz bandwidth,10v/s slew rate ltc6244 dual 50mhz cmos op amp low noise, rail-to-rail out, ms8 and dfn packages single supply strain gauge ampli? er 60812 ta02 + 0.01 f 350 350 100k a v = 1001 sensor: omega sg-3/350-ly41 strain gauge lt1790b 1.25v 1.25v 100 9.76m 500k cmrr trim 3v 3.2v + 0.1 f 0.1 f 10m 10m 10m 3v 10k 1/2 ltc6081 1/2 ltc6081

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